Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes

Author

Tugbawa, Tamba E. ; Park, Tae H. ; Boning, Duane S.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

fYear

2002

fDate

2002

Firstpage

167

Lastpage

169

Abstract

We present a characterization and modeling methodology for chip-level simulation of pattern dependencies in the fabrication of copper interconnects. The methodology integrates semi-empirical models for copper CMP and copper plating processes, and uses a specialized test mask and design of experiments for calibration purposes. We demonstrate the methodology with a four step copper CMP process and a superfill electroplating technology example.

Keywords

chemical mechanical polishing; copper; design of experiments; electroplating; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit testing; masks; semiconductor process modelling; Cu; calibration; characterization methodology; copper CMP; copper chemical mechanical polishing; copper electroplating; copper interconnect; copper plating processes; design of experiments; four step copper CMP process; integrated chip-scale simulation; modeling methodology; pattern dependencies; semi-empirical models; superfill electroplating technology; test mask; Calibration; Chemical processes; Chemical technology; Copper; Laboratories; Semiconductor device modeling; Slurries; Surface resistance; Surface topography; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014922

Filename

1014922