DocumentCode :
1900465
Title :
Scaling trends for the on chip power dissipation
Author :
Chandra, Girish ; Kapur, Pawan ; Saraswat, Krishna C.
Author_Institution :
CISX 326, Stanford Univ., CA
fYear :
2002
fDate :
2002
Firstpage :
170
Lastpage :
172
Abstract :
Power is increasingly becoming a performance bottleneck for high-end microprocessors. This work systematically quantifies various sources of on-chip power dissipation and predicts change in their relative contribution with scaling, thus, identifying key problematic areas. It is found that interconnects account for the single largest component of power and are likely to remain at formidable proportions in the future. However, other components are also rapidly becoming important.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit modelling; microprocessor chips; high-end microprocessors; interconnects; on-chip power dissipation; performance bottleneck; relative power dissipation contribution; scaling trends; Capacitance; Clocks; Frequency; Logic devices; Microprocessors; Power dissipation; Read-write memory; Repeaters; Stochastic processes; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
Type :
conf
DOI :
10.1109/IITC.2002.1014923
Filename :
1014923
Link To Document :
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