Title : 
A Combined VLSI Architecture for Nonlinear Image Processing Filters
         
        
            Author : 
Hernandez, Orlando J. ; Keohane, Tara ; Steponanko, Julia
         
        
            Author_Institution : 
Dept. of Electr. & Comput. Eng., New Jersey Coll., NJ
         
        
        
            fDate : 
March 31 2005-April 2 2005
         
        
        
        
            Abstract : 
In recent years, nonlinear methods and techniques have emerged as intensive research topics in the fields of signal, image, and video processing. This paper describes the combined design of high performance architectures for different filter algorithms and structures used in nonlinear image processing targeted at computer vision. These types of filters include weighted order statistics (WOS), stack, nonlinear mean, Teager, polynomial and rational filters. This architecture is suitable for real time and high quality video imaging tasks and VLSI implementations. These architectures can be used as coprocessor subsystems, integrated with other modules, to form an overall high performance imaging pipe in a system-on-a-chip platform
         
        
            Keywords : 
VLSI; computer vision; coprocessors; nonlinear filters; polynomials; statistics; system-on-chip; Teager; VLSI architecture; computer vision; coprocessor subsystems; nonlinear image processing filters; polynomial; rational filters; system-on-a-chip platform; video imaging; weighted order statistics; Algorithm design and analysis; Computer architecture; Computer vision; Coprocessors; Filters; Image processing; Polynomials; Signal processing; Statistics; Very large scale integration;
         
        
        
        
            Conference_Titel : 
SoutheastCon, 2006. Proceedings of the IEEE
         
        
            Conference_Location : 
Memphis, TN
         
        
            Print_ISBN : 
1-4244-0168-2
         
        
        
            DOI : 
10.1109/second.2006.1629361