DocumentCode
1900821
Title
The Impact of Testing on VLSI Design Methods
Author
Segers, M.T.M.
Author_Institution
Philips Research Laboratories, Eindhoven, The Netherlands
fYear
1981
fDate
22-24 Sept. 1981
Firstpage
98
Lastpage
108
Abstract
The question ``why design for testability?´´ will be answered by discussing some existing test philosophies. Exhaustive testing, functional testing and structural testing will be treated, also with regard to their usefulness for VLSI circuits. There is no general agreement on how to design for testability. Various approaches exist, and each has its specific applications. Some of these approaches will be discussed in detail, also regarding the influence of the complexity on necessary CAD tools for test pattern generation.
Keywords
Design methodology; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference, 1981. ESSCIRC '81. 7th European
Conference_Location
Freiburg, F. R. Germany
Print_ISBN
3800712385
Type
conf
Filename
5434998
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