• DocumentCode
    1900826
  • Title

    VLSI Implementations of Low-Power Leading-One Detector Circuits

  • Author

    Abed, Khalid H. ; Siferd, Raymond E.

  • Author_Institution
    Dept. of Comput. Eng., Jackson State Univ., MS
  • fYear
    2005
  • fDate
    March 31 2005-April 2 2005
  • Firstpage
    279
  • Lastpage
    284
  • Abstract
    This paper presents two approaches to design leading-one detector (LOD) circuits, which locate the leading-one position in a binary word. The first approach provides fast leading-one detectors (LODs), and the second emphasizes the design of novel hardware-efficient and low-power LODs. Each approach is used to obtain 0.6 mum CMOS VLSI implementations of 16-, 32-, and 64-bit LOD circuits. Simulations of the 16-, 32-, and 64-bit fast LODs run at 310, 265, and 215 MHz, respectively. The 16-, 32-, and 64-bit low-power LODs consume 14.85, 44.70, and 61.67 milliwatts, respectively while operating at VDD equal to 5 volts and their maximum speed
  • Keywords
    CMOS integrated circuits; UHF integrated circuits; VHF circuits; VLSI; detector circuits; low-power electronics; 0.6 mum; 14.85 mW; 215 MHz; 265 MHz; 310 MHz; 44.70 mW; 5 V; 61.67 mW; CMOS VLSI; VLSI; low-power leading-one detector circuits; Circuit simulation; Clocks; Decoding; Detectors; Floating-point arithmetic; Frequency; Hardware; Power dissipation; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SoutheastCon, 2006. Proceedings of the IEEE
  • Conference_Location
    Memphis, TN
  • Print_ISBN
    1-4244-0168-2
  • Type

    conf

  • DOI
    10.1109/second.2006.1629364
  • Filename
    1629364
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1900826