Analog/RF Performance and Optimization of Vertical III–V Double-Gate Transistor

Parasitics engineering on a GaAs vertical transistor is analyzed. Through separate control of source/drain (S/D) spacer and underlap, the individual impact of the parasitic components is unveiled. Thicker S/D spacer improves $f_{\rm T}$ , $f_{\max }$ by reducing parasitic capacitance. Increased source-side underlap improves output resistance and gain as the virtual source point is shifted. Increased drain-side underlap improves $f_{\max }$ by reducing parasitic capacitance. Optimization of different analog/RF metrics can be easily implemented through asymmetric S/D spacer/underlap design in a vertical transistor.