An Efficient Method to Design Fractional Decimation System

This paper presents an algorithm for designing a fractional decimation system based on interpolated finite impulse response (IFIR) filter. The algorithm includes rounding and sharpening of the IFIR filter which design multiplierless decimation filter with the desired specification. Filter with no multipliers exhibits a low complexity which makes it a good candidate for Software Radio (SR) application. Further, the proposed structure is implemented in SPARTAN-3 family of Xilinx Field Programmable Gate Array (FPGA). The complexity is decreased by replacing the multipliers with add and shift algorithm of fixed point multiplication.