Title :
Process integration of Cu metallization and ultra low k (k=2.2)
Author :
Cheng, Chuan-cheng ; Hsia, Wei-Jen ; Pallinti, Jayanthi ; Neumann, Sarah ; Koh, Jerry ; Li, Pamela ; Zhu, Mei ; Lu, Michael ; Cui, Hao ; Fujimoto, Toshikazu ; Catabay, Wilbur ; Wright, Peter
Author_Institution :
Process Technol. Dept., LSI Logic Corp., Santa Clara, CA, USA
Abstract :
The first process integration of Cu metallization and next generation CVD ultra low k (Trikon Orion ULK, k=2.2) is presented. The current process condition for a 130 nm node Cu/lowk (k=2.9) process is applied to Cu/ULK and found to be suitable without major modifications. The comparison of post CMP measurement (dishing, erosion, peeling, and scratch) show no significant variation between control (k=2.9) and ULK. The electrical data indicates the successful integration of Cu and ULK. The interconnect capacitance is expected to reduce 20% at 0.1 μm technology node using the ULK film.
Keywords :
CVD coatings; chemical mechanical polishing; copper; dielectric thin films; metallisation; 0.1 micron; 130 nm; CMP; CVD; Cu; Cu metallization; dishing; erosion; interconnect capacitance; peeling; process integration; scratching; ultra-low-k film; Chemistry; Delay; Dielectric constant; Dielectric materials; Etching; Inspection; Large scale integration; Logic; Metallization; Silicon carbide;
Conference_Titel :
Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International
Print_ISBN :
0-7803-7216-6
DOI :
10.1109/IITC.2002.1014950
