Copper damascene interconnects for the 65 nm technology node: a first look at the reliability properties

Author

Steinlesberger, G. ; von Glasow, A. ; Engelhardt, M. ; Schindler, G. ; Hönlein, W. ; Holz, M. ; Bertagnolli, E.

Author_Institution

Corporate Res., Infineon Technol., Munich, Germany

fYear

2002

fDate

2002

Firstpage

265

Lastpage

267

Abstract

Copper interconnects with end-of-roadmap feature sizes, fabricated in damascene technology, were electrically and thermally stressed to assess reliability performance. The maximum current carrying capability of 63 nm wide copper wires was found to be a factor of 2 higher when compared with current technologies. The impact of the Cu seed layer thickness on activation energy and stress voiding is discussed. The first lifetime estimations, assuming the ITRS roadmap requirements, were also made.

Keywords

copper; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; thermal stresses; voids (solid); 63 nm; 65 nm; Cu; Cu seed layer thickness; ITRS roadmap requirements; activation energy; copper damascene interconnects; damascene technology; electrically stressed interconnects; end-of-roadmap feature sizes; lifetime estimations; maximum current carrying capability; reliability performance; reliability properties; stress voiding; technology node; thermally stressed interconnects; Conductivity; Copper; Life estimation; Lifetime estimation; Lithography; Space technology; Temperature measurement; Testing; Thermal stresses; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International

Print_ISBN

0-7803-7216-6

Type

conf

DOI

10.1109/IITC.2002.1014952

Filename

1014952