Title :
A CMOS gate array with dynamic-termination GTL I/O circuits
Author :
Kudoh, Junya ; Takahashi, Toshiro ; Umada, Yukio ; Kimura, Masaharu ; Yamamoto, Shigeru ; Ito, Youichi
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A 530 kG gate array with novel GTL I/O circuits has been developed using 0.5 μm CMOS triple-metal-layer process technology. The I/O circuit of a push-pull output driver and a dynamic termination receiver can transmit 250 Mb/s data through a long stub line which is connected to a terminated bus line. IDDQ testability is designed for the differential receiver without any delay time overheads
Keywords :
CMOS logic circuits; delays; logic arrays; logic testing; 0.5 micron; 250 Mb/s data; 250 Mbit/s; CMOS gate array; IDDQ testability; delay time overheads; differential receiver; dynamic termination receiver; dynamic-termination GTL I/O circuits; push-pull output driver; stub line; terminated bus line; triple-metal-layer process technology; CMOS process; CMOS technology; Connectors; Driver circuits; Frequency; Impedance; MOSFETs; Microcomputers; Reflection; Ultra large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-7165-3
DOI :
10.1109/ICCD.1995.528786
