A High-Performance Scheduling Algorithm Based on Packet Sto

Author

Qu, Jing ; Hu, Ximing ; Yi, Peng ; Zhang, Xingming ; Wang, Binqiang

Author_Institution

R&D Center, Nat. Digital Switching Syst. Eng. &Technol., Zhengzhou

fYear

2005

fDate

27-29 Nov. 2005

Firstpage

44

Lastpage

44

Abstract

The combined input-crosspoint-queued (CICQ) crossbar switch is becoming very attractive for the design of high performance routers due to the unique features it offers. A plethora of distributed scheduling algorithms with low complexities have been proposed for this architecture. However, the size of crosspoint buffer (CB) is limited in a single chip by today´s ASIC technology. In this paper, we propose a novel scheduling scheme named the exceed threshold first round robin (ETFRR) which aims at reducing buffer size of CB. This scheme can reduce the packet loss ratio and improve packet storage ratio efficiently.

Keywords

application specific integrated circuits; buffer circuits; computer networks; processor scheduling; queueing theory; telecommunication network routing; ASIC technology; combined input-crosspoint-queued crossbar switch; crosspoint buffer; distributed scheduling algorithms; exceed threshold first round robin; packet loss ratio; packet storage ratio; routers; Application specific integrated circuits; Buffer storage; Logic; Research and development; Round robin; Scheduling algorithm; Switches; Switching systems; Systems engineering and theory; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Semantics, Knowledge and Grid, 2005. SKG '05. First International Conference on

Conference_Location

Beijing

Print_ISBN

0-7695-2534-2

Electronic_ISBN

0-7695-2534-2

Type

conf

DOI

10.1109/SKG.2005.14

Filename

4125832