Title :
A 100 NSEC 256K Dynamic RAM
Author :
Yamamoto, H. ; Inagaki, Y. ; Kudoh, O. ; Murao, Y. ; Mitake, K. ; Tameda, M. ; Kobayashi, K. ; Mano, T.
Author_Institution :
Nippon Electric Co., Ltd., Sagamihara, Japan
Abstract :
The high speed 100ns 256K Dynamic MOS RAM has been developed, employing polysilicon and molybdenum (Mo) gates technology, and assembled in a standard 300mi1 16pin DIP.
Keywords :
Assembly; Capacitors; Communication standards; DRAM chips; Electronics packaging; Integrated circuit interconnections; Laboratories; Parasitic capacitance; Random access memory; Read-write memory;
Conference_Titel :
Solid State Circuits Conference, 1981. ESSCIRC '81. 7th European
Conference_Location :
Freiburg, F. R. Germany
