DocumentCode :
1901695
Title :
Implementing a STARI chip
Author :
Greenstreet, Mark R.
Author_Institution :
Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
fYear :
1995
fDate :
2-4 Oct 1995
Firstpage :
38
Lastpage :
43
Abstract :
STARI is a high-speed signaling technique that uses both synchronous and self-timed circuits. To demonstrate STARI, a chip has been fabricated using the MOSIS 2μ CMOS process. In a simple test fixture, it operates at data rates of 120 Mbits/sec over a pair of wires. Because STARl uses both synchronous and self-timed circuits, it provides an opportunity to compare these two design methods. The synchronous circuits of the STARI chip achieve rates of operation two to three times those of the self-timed circuits. However, the self-timed FIFO in the receiver provides robust compensation for clock skew that could not be achieved with synchronous circuitry alone. Thus, the STARI chip demonstrates advantages of combining these two design techniques
Keywords :
CMOS digital integrated circuits; digital signal processing chips; timing circuits; 2 micron; MOSIS 2μ CMOS process; STARI chip; clock skew; high-speed signaling technique; robust compensation; self-timed FIFO; self-timed circuits; synchronous circuits; Bandwidth; CMOS process; Circuit testing; Clocks; Communication system control; Delay; Design methodology; Fixtures; Transmitters; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-8186-7165-3
Type :
conf
DOI :
10.1109/ICCD.1995.528788
Filename :
528788
Link To Document :
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