DocumentCode
1901852
Title
A monolithic CMOS 10.4-GHz phase locked loop
Author
Dong-Jun Yang ; O, K.
Author_Institution
Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
fYear
2002
fDate
13-15 June 2002
Firstpage
36
Lastpage
37
Abstract
A 10.4-GHz PLL with a 256/257 dual modulus prescaler implemented in a 0.18-/spl mu/m CMOS process is presented. The prescaler with a 4/5 synchronous counter operates up to 14 GHz. The counter achieves this by using feedback. The phase noise levels of the PLL and VCO at a 3-MHz offset with I/sub VCO/=8.1 mA are -122 dBc/Hz. The PLL operates between 9.7 10.4 GHz, while drawing 34 mA at V/sub DD/=1.8 V.
Keywords
CMOS integrated circuits; circuit feedback; field effect MMIC; integrated circuit noise; mixed analogue-digital integrated circuits; phase locked loops; phase noise; 0.18 micron; 1.8 V; 34 mA; 9.7 to 10.4 GHz; CMOS PLL; VCO; dual modulus prescaler; feedback; monolithic phase locked loop; synchronous counter; CMOS process; Counting circuits; Feedback; Filters; Flip-flops; Frequency conversion; MOSFETs; Phase locked loops; Phase noise; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015037
Filename
1015037
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