1.2 Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique

Author

Fujimura, Y. ; Takahashi, T. ; Toyoshima, S. ; Nagashima, K. ; Baba, J. ; Matsumoto, T.

Author_Institution

Device Dev. Center, Htachi Ltd., Tokyo, Japan

fYear

2002

fDate

13-15 June 2002

Firstpage

58

Lastpage

59

Abstract

We have developed a simultaneous bidirectional transceiver logic -composed of a transmitter with an output level feedback pre-buffer and a receiver with two sense amplifiers and a hazard-free selector - that reduces the data jitter originating from three voltage level transmission. We also developed a bit deskew technique that takes into account the influence of switching noise to obtain the maximum timing margin in multi-pin operation. Stable throughput of 1.2 Gbps/pin was achieved in simultaneous 81-pin operation using a printed circuit board.

Keywords

integrated circuit noise; integrated logic circuits; timing jitter; transceivers; 1.2 Gbit/s; bit deskew technique; data jitter; hazard-free selector; multi-pin operation; output level feedback pre-buffer; printed circuit board; receiver; sense amplifier; simultaneous bidirectional transceiver logic; switching noise; three voltage level transmission; timing margin; transmitter; Circuit noise; Jitter; Logic; Output feedback; Printed circuits; Throughput; Timing; Transceivers; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015044

Filename

1015044