Title :
CMOS Digital Pixel for Binary Morphological Edge Segmentation
Author :
Garcia-Lamont, Jair ; Vazquez-Acosta, Edgar N. ; Sanchez-Diaz, Guillermo ; Gonzalez-Vidal, Jose L.
Author_Institution :
Univ. Autonoma del Estado de Hidalgo, Pachuca
Abstract :
A digital pixel for binary morphological image processing is presented. The pixel is designed to be integrated into a vision chip with parallel architecture, in order to compute edge segmentation. The pixel contains 11 transistors working with analog signal and 20 transistor working with digital signal; pixel layout size is 115.2 mum times 89.4 mum; fill factor is 1.85%; 1.2 mum CMOS standard technology from AMI is used for prototyping; random noise is 2.7 mV; peak analog output signal to noise ratio is 44 dB; optical dynamic range is 53 dB; dark current is 11 mV/s; processing time is 3.5 ms; maximum power dissipation is 264 muW.
Keywords :
CMOS integrated circuits; digital signal processing chips; edge detection; image segmentation; random noise; CMOS digital pixel; analog signal; binary morphological edge segmentation; binary morphological image processing; digital signal; parallel architecture; pixel layout size; power 264 muW; random noise; size 1.2 micron; vision chip; CMOS process; CMOS technology; Computer vision; Concurrent computing; Image processing; Image segmentation; Optical noise; Parallel architectures; Pixel; Signal processing;
Conference_Titel :
Electronics, Robotics and Automotive Mechanics Conference, 2007. CERMA 2007
Conference_Location :
Morelos
Print_ISBN :
978-0-7695-2974-5
DOI :
10.1109/CERMA.2007.4367697
