• DocumentCode
    1902097
  • Title

    Wafer Scale Integration: A New Approach

  • Author

    Aubusson, R.C. ; Catt, I.

  • Author_Institution
    Middlesex Polytechnic, Queensway, Enfield, Middlesex, EN3 4SF, England.
  • fYear
    1977
  • fDate
    20-22 Sept. 1977
  • Firstpage
    76
  • Lastpage
    78
  • Abstract
    A new approach to full slice technology is described in relation to other techniques for creating multiple-chip memories. A fixed interconnection, fault-tolerant procedure capable of creating a 1 Megabit monolithic semiconductor memory is presented.
  • Keywords
    Circuit faults; Circuit testing; Costs; Fault tolerance; Integrated circuit interconnections; Integrated circuit reliability; LAN interconnection; Semiconductor memory; Wafer scale integration; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference, 1977. ESSCIRC '77. 3rd European
  • Conference_Location
    Ulm, F.R. Germany
  • Print_ISBN
    380071132X
  • Type

    conf

  • Filename
    5435059
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1902097