Title :
Wafer Scale Integration: A New Approach
Author :
Aubusson, R.C. ; Catt, I.
Author_Institution :
Middlesex Polytechnic, Queensway, Enfield, Middlesex, EN3 4SF, England.
Abstract :
A new approach to full slice technology is described in relation to other techniques for creating multiple-chip memories. A fixed interconnection, fault-tolerant procedure capable of creating a 1 Megabit monolithic semiconductor memory is presented.
Keywords :
Circuit faults; Circuit testing; Costs; Fault tolerance; Integrated circuit interconnections; Integrated circuit reliability; LAN interconnection; Semiconductor memory; Wafer scale integration; Wiring;
Conference_Titel :
Solid State Circuits Conference, 1977. ESSCIRC '77. 3rd European
Conference_Location :
Ulm, F.R. Germany
