A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit

Author

Iwata, T. ; Hirata, T. ; Sugimoto, H. ; Kimura, H. ; Yoshikawa, T.

Author_Institution

Adv. LSI Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

2002

fDate

13-15 June 2002

Firstpage

82

Lastpage

83

Abstract

A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.

Keywords

CMOS digital integrated circuits; clocks; high-speed integrated circuits; synchronisation; 0.18 micron; 5 Gbit/s; BER; CDR; CMOS; clock and data recovery; data acquisition; frequency tolerance; frequency tolerant multi phase clock recovery circuit; multi phase gated VCO; multi-channel high-speed serial interface; plesiochronous clocking capability; random incoming data; CMOS technology; Circuits; Clocks; Computer buffers; Delay; Frequency; Phase locked loops; Space vector pulse width modulation; Switches; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015052

Filename

1015052