Design and Optimization of Ethernet Access System for Receiving Frames of Ethernet Based on FPGA

Author

En, Shao ; Dongming, Yuan ; Jinchun, Gao ; Yuanan, Liu ; Hefei, Hu

Author_Institution

Beijing Univ. of Posts & Telecommun., Beijing, China

Volume

3

fYear

2012

fDate

23-25 March 2012

Firstpage

129

Lastpage

133

Abstract

The purpose of this paper is to design and develop an implementation for the underlying data reception on Field Programmable Gate Arrays (FPGA) by top-down structured design. In this paper, we optimize the receiving data function of underlying Ethernet access device, reducing the requirement of the Inter-Packet Gap (IPG) for flow control. It is shown by the test that Ethernet access device don´t need IPG for flow control any longer after our optimization.

Keywords

field programmable gate arrays; local area networks; protocols; Ethernet access device; Ethernet access system design; Ethernet access system optimization; Ethernet receiving frames; FPGA; IEEE 802.3 protocol; data reception; field programmable gate array; flow control; interpacket gap; receiving data function optimization; top-down structured design; Clocks; Delay; EPON; Field programmable gate arrays; IEEE 802.3 Standards; Random access memory; Synchronization; Ethernet access; FPGA; IPG; Medium Access Control;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Electronics Engineering (ICCSEE), 2012 International Conference on

Conference_Location

Hangzhou

Print_ISBN

978-1-4673-0689-8

Type

conf

DOI

10.1109/ICCSEE.2012.200

Filename

6188182