A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

Author

Chang, K.-Y.K. ; Wei, J. ; Li, S. ; Li, Y. ; Donnelly, K. ; Huang, C. ; Sidiropoulos, S.

Author_Institution

Rambus Inc, Los Altos, CA, USA

fYear

2002

fDate

13-15 June 2002

Firstpage

88

Lastpage

91

Abstract

A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.

Keywords

CMOS integrated circuits; VLSI; data communication equipment; digital communication; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; transceivers; 0.13 micron; 0.4 to 4 Gbit/s; 390 mW; 400 mV; BER; CMOS technology; bit error rate; dual on-chip regulators; high-speed point-to-point links; low power consumption; quad high-speed transceiver cell; regulated dual-loop PLL; CMOS technology; Clocks; Energy consumption; Frequency conversion; Phase locked loops; Regulators; Resistors; Transceivers; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015054

Filename

1015054