A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

Author

Young-Soo Sohn ; Seung-Joon Bae ; Hong-June Park ; Soo-In Cho

Author_Institution

Dept. of Electr. Eng., Pohang Inst. of Sci. & Technol., South Korea

fYear

2002

fDate

13-15 June 2002

Firstpage

92

Lastpage

93

Abstract

A CMOS DFE (decision feedback equalization) receiver with a negligible overhead in chip area and power consumption was implemented by cross-coupling the outputs of a conventional 2-way interleaving receiver to the other side of the input. Application of this receiver to the SSTL interface channel showed the increase of sampling time window by 60 /spl sim/120% at data rates from 800 Mbps up to 1.2 Gbps. Chip area and power consumption are 80/spl times/100 /spl mu/m and 2.5 mW respectively with a 0.25 /spl mu/m 1-poly 5-metal CMOS process at the supply voltage of 2.5 V.

Keywords

CMOS integrated circuits; data communication equipment; decision feedback equalisers; mixed analogue-digital integrated circuits; receivers; 0.25 micron; 1-poly 5-metal CMOS process; 2-way interleaving receiver; 2.5 V; 2.5 mW; 800 Mbit/s to 1.2 Gbit/s; CMOS DFE receiver; SSTL interface channel; decision feedback equalization receiver; extended sampling time window; Bandwidth; Decision feedback equalizers; Energy consumption; Feedback circuits; Flip-flops; Interleaved codes; Random access memory; Sampling methods; Transmitters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015055

Filename

1015055