High speed multiply-accumulator coprocessor realized for digital filters

Author

RahulNarasimhan, A. ; Subramanian, R. Siva

Author_Institution

Sch. of Electron. Eng., VIT Univ., Chennai, India

fYear

2015

fDate

5-7 March 2015

Firstpage

1

Lastpage

4

Abstract

In this paper, an optimized co-processor unit, designed specifically for executing the DSP application is proposed. It can be used as a co-processor for the ACORN ARM processor. The co-processor comprises of one MAC unit, control unit, a 32 bit output registers and register files for storing the input values and other co-efficient. The co-processor is designed to execute a FIR filter. Vedic multiplier and booth multiplier has been used in the MAC unit and comparison is done based on the power, speed and area. The MAC unit has two 16 bit input, one 32 bit input and one 32 bit output.

Keywords

FIR filters; coprocessors; flip-flops; multiplying circuits; ACORN ARM processor; DSP application; FIR filter; MAC unit; Vedic multiplier; booth multiplier; digital filters; high speed multiply-accumulator coprocessor; optimized coprocessor unit; output registers; register files; Engines; Irrigation; Reduced instruction set computing; ARM processor; Multiply-accumulate; Vedic multipliers; coprocessor; digital filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-6084-2

Type

conf

DOI

10.1109/ICECCT.2015.7226159

Filename

7226159