DocumentCode
1902286
Title
Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology
Author
Ortolland, C. ; Orain, S. ; Rosa, J. ; Morin, P. ; Arnaud, F. ; Woo, M. ; Poncet, A. ; Stolk, P.
Author_Institution
Philips Semicond., Crolles, France
fYear
2004
fDate
21-23 Sept. 2004
Firstpage
137
Lastpage
140
Abstract
In this paper, we present a study of the effects of strained contact etch stop layer on 65 nm CMOS transistor performance. It is found that the nitride layer above the transistor can improve the transistor drive current by 8.5% for NMOS and 6% for PMOS. By combining a complete electrical analysis, mechanical modeling and quantum simulations, we have obtained a detailed understanding of how transistor layout rules influence the strain enhancements.
Keywords
MOSFET; internal stresses; isolation technology; semiconductor device models; 65 nm; CMOS technology; CMOS transistor; NMOS transistors; PMOS transistors; STI; etch-stop layers; mechanical stress; process induced strain; strain enhancements; strained contact etch stop layer; transistor drive current; transistor layout rules; transistor nitride layer; CMOS process; CMOS technology; Capacitive sensors; Contacts; Etching; MOS devices; Semiconductor device modeling; Silicon; Tensile strain; Tensile stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN
0-7803-8478-4
Type
conf
DOI
10.1109/ESSDER.2004.1356508
Filename
1356508
Link To Document