A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

Author

Matano, T. ; Takai, Yoshiaki ; Takahashi, Tatsuro ; Sakito, Y. ; Takaishi, Y. ; Fujisawa, Hiroyuki ; Kubouchi, S. ; Narui, S. ; Arai, Kenta ; Morino, M. ; Nakamura, Mitsutoshi ; Miyatake, S. ; Sekiguchi, Takeshi ; Koyama, Koichi ; Miyazawa, K.

Author_Institution

ELPIDA Memory Inc.,, Kanagawa, Japan

fYear

2002

fDate

13-15 June 2002

Firstpage

112

Lastpage

113

Abstract

We developed a 1-Gb/s/pin 512-Mb DDRII SDRAM composed of a digital delay-locked loop (DLL) and a slew-rate controlled output buffer. The digital DLL has a frequency divider for the DLL input, which performs at a operating frequency of up to 500 MHz at 1.6 V, and it provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, is standby-current-free, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5 mm/sup 2/ 512 Mb device.

Keywords

CMOS memory circuits; DRAM chips; delay lock loops; high-speed integrated circuits; 0.8 to 1.6 V; 1 Gbit/s; 14 ps; 500 MHz; 512 Mbit; DDRII SDRAM; current mirror type interpolator; digital DLL; digital delay-locked loop; frequency divider; slew-rate-controlled output buffer; synchronous DRAM; Ambient intelligence; Automatic control; Capacitance; Clocks; Control systems; Driver circuits; Frequency conversion; Impedance; Low voltage; SDRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015058

Filename

1015058