DocumentCode :
1902391
Title :
A low-noise 2-GB/s 256-Mb packet-based DRAM with a robust array power supply
Author :
Kee-Won Kwon ; Byung-Sick Moon ; Changhyun Kim ; Soo-In Cho
Author_Institution :
DRAM Design III, Samsung Electron. Co. LTD., Gyunggi, South Korea
fYear :
2002
fDate :
13-15 June 2002
Firstpage :
116
Lastpage :
117
Abstract :
With a robust array power supply, the array noise is remarkably suppressed in 256-Mb packet-based DRAM. The array power supply is equipped with direct driver discharge, Vgs clamp, high-VCC compensator, and low-VCC Vgs booster. The VCCA drop and overshoot are improved from 133 mV to 70 mV and from 260 mV to 120 mV, respectively, as all these features are included. The tranquil VCCA results in active restoration improvement by 3.0 ns in the full chip performance. The suppression of the VCCA overshoot makes high speed operation reliable owing to rapid column precharge. The power consumption by the VCCA generator is also reduced by 35% because of the time-variant DC current control.
Keywords :
CMOS memory circuits; DRAM chips; VLSI; high-speed integrated circuits; integrated circuit noise; power supply circuits; 2 GB/s; 256 Mbit; Vgs clamp; array noise suppression; direct driver discharge; dynamic RAM; high speed operation; high-VCC compensator; low-VCC Vgs booster; low-noise DRAM; packet-based DRAM; rapid column precharge; robust array power supply; time-variant DC current control; Distributed power generation; Driver circuits; Energy consumption; Mesh generation; Power generation; Power grids; Power supplies; Random access memory; Robustness; Standby generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
Type :
conf
DOI :
10.1109/VLSIC.2002.1015060
Filename :
1015060
Link To Document :
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