DocumentCode
1902404
Title
1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture
Author
Fujisawa, H. ; Takahashi, T. ; Yoko, H. ; Fujii, I. ; Takai, Y. ; Nakamura, M.
Author_Institution
Dev. Div., Elpida Memory Inc., Kanagawa, Japan
fYear
2002
fDate
13-15 June 2002
Firstpage
118
Lastpage
119
Abstract
A low impedance hierarchical I/O architecture designed to realize both high-speed and low-voltage DRAMs is presented. In this architecture, use of the divided I/O lines over the memory cells reduces the load of I/O lines by 50% and enables a 2.2 ns reduction of the read/write cycle time. By combining the distributed data transfer scheme, we achieved a 4 ns reduction of the access time to 8 ns and 1-Gb/s/pin operation with a 1.8-V power supply in a multi-Gb DRAM.
Keywords
CMOS memory circuits; DRAM chips; VLSI; high-speed integrated circuits; memory architecture; 1 Gbit/s; 1.8 V; 8 ns; LV dynamic RAM; distributed data transfer scheme; divided I/O lines; high-speed DRAMs; low impedance hierarchical I/O architecture; low-voltage DRAMs; multi-gigabit DRAM design; Circuit simulation; Driver circuits; Flexible printed circuits; Fluctuations; Impedance; Operational amplifiers; Parasitic capacitance; Power supplies; Prefetching; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015061
Filename
1015061
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