Title :
SOI-optimized 64-bit high-speed CMOS adder design
Author :
Jae-Joon Kim ; Joshi, R. ; Ching-Te Chuang ; Roy, K.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Presents a high-speed 64-bit hybrid carry-lookahead/carry-select adder in 0.1 /spl mu/m partially depleted silicon-on-insulator (PD/SOI) technology with a critical path delay of 346 ps. Sense-amplifier based differential logic with source follower evaluation tree is used for fast generation of 8-bit group carry. Floating body PD/SOI shows 24% performance improvement over bulk CMOS for the 8-bit group carry generating circuit. We also show that the proposed circuit is robust to noise induced by floating body effect in PD/SOI.
Keywords :
CMOS logic circuits; adders; carry logic; delays; differential amplifiers; high-speed integrated circuits; silicon-on-insulator; 0.1 micron; 346 ps; 64 bit; 8 bit; carry generating circuit; carry-lookahead/carry-select adder; critical path delay; floating body effect; high-speed CMOS adder design; partially depleted silicon-on-insulator; sense-amplifier based differential logic; source follower evaluation tree; Adders; Bismuth; CMOS logic circuits; Circuit noise; Hybrid power systems; Logic circuits; Logic devices; Noise robustness; Signal generators; Silicon on insulator technology;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015062
