Title :
A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core
Author :
Mathew, S. ; Anders, M. ; Krishnamurthy, R. ; Borkar, S.
Author_Institution :
Circuits Res., Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes a 32-bit Address Generation Unit (AGU) designed for 4 GHz operation in 1.2 V, 130 nm technology. The AGU utilizes a 152 ps dual-V, sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. The semidynamic implementation enables an average energy profile similar to static CMOS, with good sub-130 nm scaling trend.
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; VLSI; adders; high-speed integrated circuits; microprocessor chips; 1.2 V; 130 nm; 152 ps; 32 bit; 4 GHz; CMOS technology; address generation unit; delay reduction; high-performance microprocessors; interconnect density reduction; low active energy leakage component; semidynamic implementation; sparse-tree adder core; Adders; CMOS technology; Clocks; Delay; Energy efficiency; Integrated circuit interconnections; Logic circuits; Microprocessors; Multiplexing; Rails;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015063
