A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

Author

Cheung, V.S.-L. ; Luong, H.C. ; Wing-Hung Ki

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2002

fDate

13-15 June 2002

Firstpage

140

Lastpage

143

Abstract

Based on only half-delay switched-capacitor integrators, a 7/sup th/-order IF-filter and a 3/sup rd/-order /spl Sigma//spl Delta/ modulator using a novel noise-shaping extension technique are implemented for a Bluetooth receiver in a 0.35-/spl mu/m CMOS process. At a 1-V supply, the quadrature IF circuitry achieves a measured IIP3 of -3 dBm at a nominal gain of 24 dB through a 48-dB variable-gain control with a power dissipation of 3.5 mW.

Keywords

CMOS analogue integrated circuits; VLSI; biquadratic filters; frequency hop communication; integrating circuits; low-pass filters; operational amplifiers; radio receivers; sigma-delta modulation; spread spectrum communication; switched capacitor filters; 0.35 micron; 1 V; 24 dB; 3.5 mW; Bluetooth receiver; CMOS IF circuitry; CMOS process; half-delay SC integrators; noise-shaping extension technique; seventh-order IF filter; sigma-delta modulator; switched-capacitor integrators; switched-opamp quadrature IF circuitry; third-order /spl Sigma//spl Delta/ modulator; Band pass filters; Bluetooth; CMOS process; Capacitors; Consumer electronics; Energy consumption; Noise shaping; Power dissipation; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015067

Filename

1015067