Junction leakage analysis using Scanning Capacitance Microscopy

We develop a technique to study junction leakage in an advanced complementary metal oxide semiconductor (CMOS) device using Scanning Capacitance Microscopy (SCM). Progressive metal cuts and direct probing were performed to isolate the affected test structure. A reverse bias voltage was applied across the n-well and p-type diffusion layer. The current-voltage (I-V) curves obtained confirmed presence of leakage in the test structures. The SCM data revealed that the marginal leakage current is due to higher n-well doping level of the device compared to the control. Furthermore, the diode-tunnelling equation was simulated and the results are in good agreement with empirical data. The SCM technique can therefore be very useful for defect localization and physical failure analysis for samples without interconnects or electrodes to aid in root cause identification.