Title :
A new buses scheme for fast inner-product computation
Author :
Lin, R. ; Olariu, S.
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Geneseo, NY, USA
fDate :
31 Oct-2 Nov 1994
Abstract :
In this paper we adopt and modify the shift switching mechanism to propose a novel VLSI inner product processor architecture involving broadcasting on short buses, i.e. buses with no more than 8 switches each. The computation of the inner product of two positive vectors of N item each consisting of m bits takes only [log3 (mN/7)]+1 broadcasts, plus a carry-save and a carry-propagate additions
Keywords :
VLSI; adders; carry logic; digital arithmetic; multiplying circuits; shift registers; system buses; VLSI inner product processor architecture; broadcasting; carry-propagate additions; carry-save; fast inner-product computation; positive vectors; shift switching mechanism; short buses; Broadcasting; Compressors; Computer architecture; Computer science; Contacts; Counting circuits; Delay effects; Delay estimation; Switches; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-6405-3
DOI :
10.1109/ACSSC.1994.471688
