Title :
101 GHz fTmax SiGe:C HBT integrated into 0.25 μm CMOS with conventional LOCOS isolation
Author :
Yamagata, Hideo ; Yanagawa, Shusah ; Komoto, Takeyoshi ; Bairo, Masaaki ; Kiyota, Yukihiro ; Yoneda, Shuji ; Oishi, Masato ; Kuranouchi, Atsushi ; Arai, Chihiro
Author_Institution :
Sony Semicond. Kyushu Corp., Kagoshima, Japan
Abstract :
A low-complexity but high-performance SiGe:C BiCMOS technology is realized by conventional simple LOCOS isolation and non-selective SiGe:C epitaxy with optimized impurity profiles. Stress-induced misfit dislocations found in the SiGe:C layer on LOCOS-patterned wafers were successfully eliminated by optimizing the epitaxial process. This, in combination with optimization of HBT impurity profiles, produced a 99% yield of 10000 parallel arrays with an fTmax of 101 GHz. The HBT has been successfully integrate in a 0.25 μm CMOS with passive components, which is suitable for low-cost RF mixed-signal applications.
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; doping profiles; epitaxial growth; heterojunction bipolar transistors; millimetre wave bipolar transistors; mixed analogue-digital integrated circuits; oxidation; radiofrequency integrated circuits; 0.25 micron; 101 GHz; CMOS; LOCOS isolation; SiGe:C; impurity profile optimization; integrated HBT; low-complexity BiCMOS technology; low-cost RF mixed-signal IC; nonselective epitaxy; stress-induced misfit dislocations; BiCMOS integrated circuits; CMOS process; Consumer electronics; Epitaxial growth; Germanium silicon alloys; Heterojunction bipolar transistors; Silicon germanium; Substrates; Thermal stresses; Wireless LAN;
Conference_Titel :
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN :
0-7803-8478-4
DOI :
10.1109/ESSDER.2004.1356524
