Title :
A 2.9ns random access cycle embedded DRAM with a destructive-read
Author :
Chomg-Lii Hwang ; Kirihata, T. ; Wordernan, M. ; Fifield, J. ; Storaska, D. ; Pontius, D. ; Fredernan, G. ; Ji, B. ; Tomashot, S. ; Sang Dhong
Author_Institution :
IBM Microelectron., Hopewell Junction, NY, USA
Abstract :
High performance devices available in a logic-based embedded DRAM process can be used to significantly improve eDRAM performance. However, random access cycle time of conventional eDRAMs remains around 6 ns. In this work, a novel destructive-read architecture that reduces the random access cycle time of an eDRAM by delaying the data write back operation to a later cycle is demonstrated. A single-ended direct sensing is employed to further speed up the random access cycle time of the eDRAM to 2.9ns.
Keywords :
DRAM chips; cellular arrays; memory architecture; 2.9 ns; data write back operation; destructive-read architecture; random access cycle embedded DRAM; random access cycle time; single-ended direct sensing; Active noise reduction; Buffer storage; Capacitors; Circuits; Logic testing; Low voltage; Random access memory; Read-write memory; Voltage control;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015077
