Investigations on possible occurrence of ballistic transport in different NMOS architectures

Author

Clerc, R. ; Ferrier, M. ; Daugé, F. ; Ghibaudo, G. ; Boeuf, F. ; Skotnicki, T.

Author_Institution

ENSERG, Grenoble, France

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

237

Lastpage

240

Abstract

This paper examines the performance of different NMOS devices (strained and unstrained bulk silicon, undoped single gate and double gate strained or unstrained SOI or SON devices) in the full ballistic regime of transport. The realism of this full ballistic transport assumption is also discussed, showing that even considering the most challenging structures, full ballistic transport will probably not be reached until channel length is lower than 10 nm.

Keywords

MOSFET; ballistic transport; carrier mobility; semiconductor device models; silicon-on-insulator; 10 nm; CMOS scaling; CMOS transistors; NMOS devices; Natori method; SOI devices; SON devices; Si; ballistic transport; carrier transport; channel length; double gate devices; quantum confinement; strained bulk silicon; undoped single gate devices; unstrained bulk silicon; Ballistic transport; CMOS technology; Electrons; Influenza; MOS devices; Microelectronics; Monte Carlo methods; Particle scattering; Quantization; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356533

Filename

1356533

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1902865