Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors

Author

Schwantes, Stefan ; Florian, Tobias ; Graf, Michael ; Dietz, Franz ; Dudek, Volker

Author_Institution

Technol. Dev., Atmel Germany GmbH, Heilbronn, Germany

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

253

Lastpage

256

Abstract

This work investigates the impact of the back gate bias on the drain breakdown behaviour of lateral high voltage SOI transistors with thick epitaxial layers. For the first time, a detailed discussion is presented giving more insight into the physical mechanisms taking place in smart power SOI devices. The results show that five different breakdown mechanisms must be considered. An analytical model that takes the back gate bias and the device parameters into account is presented and verified with a 0.8 μm 80 V SOI smart power technology.

Keywords

power MOSFET; power integrated circuits; semiconductor device breakdown; semiconductor device models; silicon-on-insulator; 0.8 micron; 80 V; SOI LDMOS transistors; back gate bias; back gate effect; breakdown mechanisms; drain breakdown; lateral high voltage SOI transistors; smart power devices; thick epitaxial layer transistors; Analytical models; Back; Doping; Electric breakdown; Electrodes; Epitaxial layers; Immune system; Isolation technology; Semiconductor process modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356537

Filename

1356537