NBTI reliability analysis for a 90 nm CMOS technology

We present a comprehensive empirical study to investigate the impact of negative bias temperature instability (NBTI) on device performance and reliability. The NBTI lifetime is calculated for different lifetime criteria such as 10% Idsat or 50 mV Vt shift for different bias conditions, temperature, duty cycles, gate length, and gate width dependence, to allow a true comparison between different methodologies. Finally, a circuit level implementation approach is presented to estimate the NBTI device level reliability at a circuit level. Therefore, the absolute threshold voltage shift is calculated and inserted into the spice level transistor model for corner simulations.