Accelerating hardware Gaussian random number generation using Ziggurat and CORDIC algorithms

This work presents an FPGA hardware implementation of a Gaussian (normal) random number generation based on Ziggurat algorithm. In Ziggurat based normal random number generator, most of the normal random numbers are generated with simple integer operations, however for small percentage of the random numbers it is required to evaluate elementary natural logarithm and exponential functions. For an accurate evaluation of these elementary functions a run-time reconfigurable CORDIC core is implemented in this work. The run-time reconfiguration is required to minimize the additional resource requirements if multiple instance of the core is used for the evaluation of the individual functions. To further speedup the random number generation process, an effective method for parallel accessing the coefficients required by the Ziggurat algorithm is presented. The implementation of the proposed architecture on Xilinx´s Kintex-7 KC705 device resulted in a throughput of 689.2 million samples per second.