Self-aligned access gate technology for compact embedded flash memories

Author

Goarin, P. ; van Schaijk, R. ; Slotboom, M. ; Tello, P.G. ; van Duuren, M. ; Akil, N. ; Baks, W.

Author_Institution

Philips Res. Leuven, Belgium

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

281

Lastpage

284

Abstract

This paper investigates an approach to solve the access gate misalignment issues linked to the poly-CMP process of compact cells. The process of this self-aligned access gate approach is be detailed and measurements demonstrate the viability of this approach and show that the issues associated with access gate misalignment, such as parameter spread among cells during source side injection programming, are gone. This paves the way for aggressively scaled low power embedded nonvolatile memories for the next CMOS generations.

Keywords

chemical mechanical polishing; flash memories; low-power electronics; random-access storage; CMOS; access gate misalignment; cell parameter spread; chemical mechanical polishing; compact cell poly-CMP process; compact embedded flash memories; low power memories; nonvolatile memories; self-aligned access gate technology; source side injection programming; CMOS logic circuits; Character generation; Distributed power generation; Flash memory; Logic devices; Logic programming; Nonvolatile memory; Power generation; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356544

Filename

1356544