Title :
Off current adjustment in ultra-thin SOI MOSFETs
Author :
Hartwich, J. ; Dreeskornfeld, L. ; Hofmann, F. ; Kretz, J. ; Landgraf, E. ; Luyken, R.J. ; Specht, M. ; Stãdele, M. ; Schulz, T. ; Rösner, W. ; Risch, L.
Author_Institution :
Corporate Res., Infineon Technol. AG, Munich, Germany
Abstract :
This work reports a detailed study of nanoscale ultra-thin (UT) SOI MOSFETs for low power applications. Partially depleted (PD) and fully depleted (FD) NMOS and PMOS devices with a wide range of gate lengths down to 25 nm and silicon thicknesses of 25 nm and 16 nm have been analysed. Gate oxide thicknesses of 2.5 nm and 1.8 nm have also been compared. We demonstrate off current adjustment by channel implantation whereby, together with work function engineering, a suitable solution for multiple Vt SOI CMOS technology could be provided.
Keywords :
MOSFET; doping profiles; ion implantation; low-power electronics; silicon-on-insulator; work function; 1.8 nm; 16 nm; 2.5 nm; 25 nm; MOSFET off current adjustment; NMOS devices; PMOS devices; channel implantation; doping concentrations; fully depleted devices; gate length; gate oxide thickness; implantation channel doping; low power MOSFET; multiple threshold voltage SOI CMOS technology; partially depleted devices; silicon thickness; ultra-thin SOI MOSFET; work function engineering; CMOS technology; Doping; Etching; Logic devices; MOS devices; MOSFETs; Modems; Silicon; Threshold voltage; Transistors;
Conference_Titel :
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN :
0-7803-8478-4
DOI :
10.1109/ESSDER.2004.1356550
