A 17 mW transmitter and frequency synthesizer for 900 MHz GSM fully integrated in 0.35-/spl mu/m CMOS

Author

Hegazi, E. ; Abidi, A.A.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

2002

fDate

13-15 June 2002

Firstpage

234

Lastpage

237

Abstract

We have presented the first fully integrated fractional-N PLL with on-chip VCO and on-chip modulator that meets the GSM specifications for both a receive mode synthesizer and a modulating PLL with 270.83 kbps GMSK data. Power consumption of the PLL is 13 mW in the RX synthesizer mode and 17 mW in the TX modulation mode. The circuit is fully digital, except for the loop filter which carries the analog VCO control voltage.

Keywords

CMOS integrated circuits; VLSI; cellular radio; digital phase locked loops; frequency synthesizers; mixed analogue-digital integrated circuits; radio transmitters; 0.35 micron; 13 mW; 17 mW; 270.83 kbit/s; 900 MHz; CMOS IC; GMSK data; GSM specifications; analog VCO control voltage; frequency synthesizer; integrated fractional-N PLL; loop filter; modulating PLL; on-chip VCO; on-chip modulator; receive mode synthesizer; transmitter; Baseband; Chirp modulation; Circuits; Frequency conversion; Frequency modulation; Frequency synthesizers; GSM; Phase locked loops; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015093

Filename

1015093