Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance

Author

Mattausch, H.J. ; Omori, N. ; Fukae, S. ; Koide, T. ; Gyoten, T.

Author_Institution

Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan

fYear

2002

fDate

13-15 June 2002

Firstpage

252

Lastpage

255

Abstract

The proposed pattern-matching engine achieves distance-measure adaptability through pattern encoding and can therefore cover a wide range of high-performance real-time applications. Key to short nearest-match times is a compact fully-parallel associative-memory core. The performance of a 9.75 mm/sup 2/ test-circuit in 0.6 /spl mu/m CMOS technology is about equivalent to a 32 bit computer with ITOPS. The test-circuit suggests possible pattern length /spl ges/768 equivalent bit, >10/sup 7/ pattern/sec throughput, <1.13% winner-input-distance error and <1.35 mW power dissipation per reference pattern.

Keywords

CMOS digital integrated circuits; Hamming codes; VLSI; content-addressable storage; digital signal processing chips; low-power electronics; parallel architectures; pattern matching; pipeline processing; real-time systems; 0.6 micron; 1.35 mW; 32 bit; Hamming distance; ITOPS; Manhattan distance; distance measure adaptability; dynamic adaptability; fully-parallel associative-memory core; fully-parallel pattern-matching engine; high-performance real-time applications; nearest-match times; pattern encoding; pattern length; power dissipation; reference pattern; throughput; winner-input-distance error; CMOS technology; Circuit testing; Encoding; Engines; Hamming distance; Hardware; Impedance matching; MOSFETs; Pattern matching; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015097

Filename

1015097