DocumentCode
1903447
Title
A new architecture of programmable digital vision chip
Author
Komuro, T. ; Kagami, S. ; Ishikawa, M.
Author_Institution
Dept. of Inf. Phys. & Comput., Univ. of Tokyo, Japan
fYear
2002
fDate
13-15 June 2002
Firstpage
266
Lastpage
269
Abstract
In this paper we propose a new architecture of digital vision chip, in which photo detectors and parallel processing elements designed in digital circuits are integrated together. In this architecture, the function to join several PEs is introduced and summation is calculated at high speed. Also, some sample algorithms and a 64/spl times/64 pixels prototype chip we developed will be described.
Keywords
computer vision; digital signal processing chips; parallel architectures; photodetectors; 4096 pixel; 64 pixel; parallel processing elements; photo detectors; processing capability; programmable digital vision chip; sample algorithms; summation; Computer architecture; Control systems; Costs; Detectors; Digital circuits; Feedback; Image sensors; Parallel processing; Pixel; Prototypes;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015100
Filename
1015100
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