Title :
Electrical characterization and modelling of high-performance SON DG MOSFETs
Author :
Harrison, S. ; Munteanu, D. ; Autran, J.L. ; Cros, A. ; Cerutti, R. ; Skotnicki, T.
Author_Institution :
L2MP, UMR CNRS 6137, Marseille, France
Abstract :
The electrical performances of highly scaled double-gate (DG) MOS transistors fabricated using a silicon-on-nothing (SON) process are presented. Very high drive current, high immunity to short-channel effects and perfect electrostatic integrity are obtained for ultra-thin and ultra-short devices, with silicon thicknesses down to 10 nm and channel lengths down to 30 nm. In addition, a dedicated compact modeling of the threshold voltage is proposed, taking into account short-channel effects, quantum mechanical confinement effects and temperature dependence. Finally, the impact of these confinement effects and ballistic transport on the operation of such ultimate devices is investigated using 2D quantum-mechanical simulations.
Keywords :
MOSFET; ballistic transport; elemental semiconductors; quantum theory; semiconductor device models; silicon; 10 nm; 2D quantum-mechanical simulations; 30 nm; SON DG MOSFET; Si; ballistic transport; channel lengths; electrostatic integrity; high drive current; high short-channel effects immunity; highly scaled double-gate MOS transistors; quantum mechanical confinement effects; silicon-on-nothing process; temperature dependence; threshold voltage compact modeling; ultra-short devices; ultra-thin devices; Ballistic transport; Bridge circuits; Epitaxial growth; Etching; MOSFETs; Potential well; Semiconductor films; Semiconductor process modeling; Silicon; Threshold voltage;
Conference_Titel :
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN :
0-7803-8478-4
DOI :
10.1109/ESSDER.2004.1356567
