DocumentCode
1903648
Title
Impact of STI-induced stress, inverse narrow width effect, and statistical VTH variations on leakage currents in 120 nm CMOS
Author
Pacha, Christian ; Martin, Benoit ; Von Arnim, Klaus ; Brederlow, Ralf ; Schmitt-Landsiedel, Doris ; Seegebrecht, Peter ; Berthold, Jorg ; Thewes, Roland
Author_Institution
Corporate Res., Infineon Technol., Munich, Germany
fYear
2004
fDate
21-23 Sept. 2004
Firstpage
397
Lastpage
400
Abstract
Leakage currents in 120 nm CMOS technology are dependent on STI-induced stress (STIS), inverse narrow-width effect (INWE), and statistical threshold voltage variations. In this paper, we analyze the impact of these effects on the gate-width dependence of the device off-current density. A threshold voltage model is proposed to describe the observed off-current minimum. STIS dominates the device behavior for large gate widths while INWE determines the off-current for gate widths below 1 μm. Statistical threshold voltage variations are relevant for minimum-sized devices.
Keywords
MOSFET; internal stresses; isolation technology; leakage currents; semiconductor device models; 1 micron; 120 nm; CMOS technology; INWE; STI-induced stress; STIS; inverse narrow width effect; leakage currents; off-current density gate-width dependence; off-current minimum; statistical threshold voltage variations; threshold voltage model; CMOS logic circuits; CMOS technology; Circuit synthesis; Current measurement; Leakage current; Logic devices; MOS devices; Semiconductor device modeling; Stress; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN
0-7803-8478-4
Type
conf
DOI
10.1109/ESSDER.2004.1356573
Filename
1356573
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