• DocumentCode
    1903801
  • Title

    Leakage-biased domino circuits for dynamic fine-grain leakage reduction

  • Author

    Seongmoo Heo ; Asanovic, K.

  • Author_Institution
    Lab. for Comput. Sci., MIT, Cambridge, MA, USA
  • fYear
    2002
  • fDate
    13-15 June 2002
  • Firstpage
    316
  • Lastpage
    319
  • Abstract
    A leakage-biased domino circuit family is proposed that maintains high speed in active mode but which can be rapidly placed into a low-leakage inactive state by using leakage currents themselves to bias internal nodes. A 32-bit Han-Carlson domino adder circuit is used to compare LB-domino with conventional single and dual Vt domino circuits. For equal delay and noise margin, the LB-domino technique gives two decades reduction in steady-state leakage energy compared to a dual-Vt technique.
  • Keywords
    CMOS logic circuits; adders; delays; integrated circuit noise; leakage currents; 32 bit; CMOS; Han-Carlson domino adder circuit; active mode; delay; dynamic fine-grain leakage reduction; internal nodes; leakage currents; leakage-biased domino circuits; low-leakage inactive state; noise margin; steady-state leakage energy; Adders; Circuit noise; Computer science; Delay; Dynamic voltage scaling; Laboratories; Leakage current; Sleep; Switches; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits Digest of Technical Papers, 2002. Symposium on
  • Conference_Location
    Honolulu, HI, USA
  • Print_ISBN
    0-7803-7310-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2002.1015114
  • Filename
    1015114