DocumentCode :
1903805
Title :
High Level System-on-Chip Design using UML and SystemC
Author :
Correa, B.A. ; Eusse, Juan Fernando ; Velez, J.F.
Author_Institution :
Univ. of Antioquia, Medellin
fYear :
2007
fDate :
25-28 Sept. 2007
Firstpage :
740
Lastpage :
745
Abstract :
Due to the increasing complexity of Systems-On-Chip (SoC), there is a need for new design methodologies in order to develop designs at higher levels of abstraction, reduce the time to market, enable functional verification and conceptual correctness at early design stages, and simplify the hardware/software partitioning tasks. Recently, there has been a growing interest in using the Unified Modeling Language (UML) together with SystemC for the design of hardware/software systems at high levels of abstraction. In this paper, an approach to translate UML 2.0 notations to the SystemC language is presented. The UML notation is extended to represent SystemC elements through the adaptation of a UML profile for SystemC. An implementation example is given to illustrate the transformation process of UML to SystemC by means of modeling an encryption system based on the Advanced Encryption Standard (AES).
Keywords :
C language; Unified Modeling Language; hardware-software codesign; system-on-chip; Advanced Encryption Standard; SystemC language; UML 2.0 notation; UML profile; Unified Modeling Language; conceptual correctness; encryption system; functional verification; hardware/software partitioning task; hardware/software system design; high level abstraction; high level system-on-chip design; Consumer electronics; Cryptography; Design methodology; Hardware; Productivity; Software systems; System-on-a-chip; Time to market; Transistors; Unified modeling language;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Robotics and Automotive Mechanics Conference, 2007. CERMA 2007
Conference_Location :
Morelos
Print_ISBN :
978-0-7695-2974-5
Type :
conf
DOI :
10.1109/CERMA.2007.4367776
Filename :
4367776
Link To Document :
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