DocumentCode :
1903861
Title :
Design-for-test techniques
Author :
Lovelace, Michael E.
Author_Institution :
Test Eng. Services & Training TEST, Kent, WA, USA
fYear :
1997
fDate :
22-25 Sep 1997
Firstpage :
390
Lastpage :
393
Abstract :
There are many Design For Test techniques, and even a brief discussion on each would require considerable timer and effort. Therefore, this paper will only address the areas of Nodal Visibility and Built-in-Test. The area of nodal visibility addresses two methods of providing signal access points, and two methods of effectively increasing the number of signal access point by using some added circuitry. The BIT application section provides a method for testing the power supply voltage monitors to verify that a power supply failure will actually result in a failure indication and an example of a parallel data acquisition system
Keywords :
built-in self test; data acquisition; design for testability; fault location; power supplies to apparatus; voltage measurement; BIT application; added circuitry; built-in-test; design for test; failure indication; nodal visibility; parallel data acquisition system; power supply failure; power supply voltage monitors; signal access points; Circuit faults; Circuit testing; Connectors; Costs; Design for testability; Frequency measurement; Hardware; Microprocessors; Monitoring; Probes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
AUTOTESTCON, 97. 1997 IEEE Autotestcon Proceedings
Conference_Location :
Anaheim, CA
Print_ISBN :
0-7803-4162-7
Type :
conf
DOI :
10.1109/AUTEST.1997.633650
Filename :
633650
Link To Document :
بازگشت