DocumentCode
1903904
Title
A 6bit 400Msps 70mW ADC using interpolated parallel scheme
Author
Ono, K. ; Shimizu, H. ; Ogawa, J. ; Takeda, M. ; Yano, M.
Author_Institution
Device & Circuit Dev. Dept., Sony Corp. Semicond. Network Co., Kanagawa, Japan
fYear
2002
fDate
13-15 June 2002
Firstpage
324
Lastpage
325
Abstract
The design of a low power 6bit, 400Msps, 1.8V CMOS ADC is presented. This ADC is based on interpolated parallel architecture in which the transistor sizes are optimized to achieve the required linearity and simultaneously minimize the power consumption. When operated at 400Msps with 1.8/2.4V power supply the ADC dissipates 70mW. The ADC is fabricated in a 0.18/spl mu/m CMOS process.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; parallel architectures; 0.18 micron; 1.8 V; 2.4 V; 6 bit; 70 mW; ADC; CMOS; interpolated parallel architecture; linearity; low power architecture; power consumption; power supply; transistor sizes; Artificial intelligence; Capacitance; Capacitors; Choppers; Circuits; Energy consumption; Frequency; Interpolation; MOS devices; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-7310-3
Type
conf
DOI
10.1109/VLSIC.2002.1015116
Filename
1015116
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