Title :
A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS
Author :
Hyde, J. ; Humes, T. ; Diorio, C. ; Thomas, M. ; Figueroa, M.
Author_Institution :
Impinj Inc, Seattle, WA, USA
Abstract :
We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves 72 dB SFDR at 250 Ms/s.
Keywords :
CMOS integrated circuits; digital-analogue conversion; 0.25 micron; 14 bit; 250 MHz; 53 mW; CMOS logic process; current-steered DAC; digital-to-analog converters; floating-gate pFETs; floating-gate trimmed DAC; onchip electrical trimming; static INL; CMOS logic circuits; CMOS process; Digital-analog conversion; Electronic switching systems; Linearity; MOSFETs; Registers; Switches; Switching circuits; Tunneling;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-7310-3
DOI :
10.1109/VLSIC.2002.1015118
