DocumentCode
1903962
Title
Novel 3-dimensional 46F2 SRAM technology with 0.294um2 S3 (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)
Author
Jang, J.H. ; Jung, S.M. ; Kang, Y.H. ; Cho, W.S. ; Moon, J.H. ; Yeo, C.D. ; Kwak, K.H. ; Choi, B.H. ; Hwang, B.J. ; Jung, W.R. ; Kim, S.J. ; Kim, J.H. ; Na, J.H. ; Lim, H. ; Jeong, J.H. ; Kinam Kim
Author_Institution
R&D Centre, Samsung Electron. Co. Ltd., Kyunggi-Do, South Korea
fYear
2004
fDate
21-23 Sept. 2004
Firstpage
445
Lastpage
448
Abstract
We have realized a 46F2 SRAM cell size of 0.294 μm2 with 80 nm technology and single stack S3 cell technology. SSTFTs and vertical node contacts are major keys in the S3 cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S3 SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S3 cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.
Keywords
CMOS memory circuits; SRAM chips; integrated circuit reliability; thin film transistors; 3D SRAM; 64 Mbit; 80 nm; ILD; Si; TFT reliability; load pMOS SSTFT; single stack S3 cell technology; stacked single-crystal Si cell; stacked single-crystal TFT; thin film transistor; vertical node contacts; CMOS technology; Circuits; Diffraction; Electric variables; Electrons; Lithography; Random access memory; Semiconductor thin films; Silicon; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Print_ISBN
0-7803-8478-4
Type
conf
DOI
10.1109/ESSDER.2004.1356587
Filename
1356587
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